The present disclosure relates to electrical testing of microelectronic structures. More specifically, in one embodiment, the present disclosure relates to the electrical testing of structures having a resistance.
In complementary metal oxide semiconductor (CMOS) technology, yield detractors such as opens and shorts in wires and interconnect vias are monitored in the manufacturing line. In early technology development, physical ground rules are explored to maximize the product yield. The guidelines for Design For Manufacturability (DFM) are given to the CMOS product design teams early in the design phase. Resistances of polysilicon (PC), metal gate, contacts, and metal wires are measured and correlated with the physical dimensions obtained from optical metrology tools. With increasing scaling, the contact resistance of contacts, e.g., the metal vias connecting the source, drain and gate terminals of the metal oxide semiconductor field effect transistors (MOSFETs) to the first metal layer (M1), has increased. The increasing resistance may reduce the MOSFET's “on” current, and can result in increased circuit delays. A large number of resistance measurements are required for testing the above mentioned design features, which can increase production cost.